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| author | Denys Vlasenko | 2022-02-10 15:38:10 +0100 |
|---|---|---|
| committer | Denys Vlasenko | 2022-02-10 15:38:10 +0100 |
| commit | 6f56fa17131b3cbb84e887c6c5fb202f2492169e (patch) | |
| tree | 3d0bbb352f7e5d56cfb7e529922a77d7176b2e42 /libbb/hash_md5_sha_x86-32_shaNI.S | |
| parent | 6a6c1c0ea91edeeb18736190feb5a7278d3d1141 (diff) | |
| download | busybox-6f56fa17131b3cbb84e887c6c5fb202f2492169e.zip busybox-6f56fa17131b3cbb84e887c6c5fb202f2492169e.tar.gz | |
libbb/sha: improve comments
Signed-off-by: Denys Vlasenko <vda.linux@googlemail.com>
Diffstat (limited to 'libbb/hash_md5_sha_x86-32_shaNI.S')
| -rw-r--r-- | libbb/hash_md5_sha_x86-32_shaNI.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/libbb/hash_md5_sha_x86-32_shaNI.S b/libbb/hash_md5_sha_x86-32_shaNI.S index afca98a..c7fb243 100644 --- a/libbb/hash_md5_sha_x86-32_shaNI.S +++ b/libbb/hash_md5_sha_x86-32_shaNI.S @@ -4,7 +4,7 @@ // We use shorter insns, even though they are for "wrong" // data type (fp, not int). // For Intel, there is no penalty for doing it at all -// (CPUs which do have such penalty do not support SHA1 insns). +// (CPUs which do have such penalty do not support SHA insns). // For AMD, the penalty is one extra cycle // (allegedly: I failed to find measurable difference). |