build system: remove KBUILD_STR()

When using GNU Make >=4.3, the KBUILD_STR() definition interferes badly
with dependency checks during build, and forces a complete rebuild every
time Make runs.

In if_changed_rule, Kconfig checks if the command used to build a file
has changed since last execution. The previous command is stored in the
generated .<file>.o.cmd file. For example applets/.applets.o.cmd defines
a "cmd_applets/applets.o" variable:

	cmd_applets/applets.o := gcc ... -D"KBUILD_STR(s)=#s" ...

Here the '#' should be escaped with a backslash, otherwise GNU Make
interprets it as starting a comment, and ignore the rest of the
variable. As a result of this truncation, the previous command doesn't
equal the new command and Make rebuilds each target.

The problem started to appear when GNU Make 4.3 (released January 2020),
introduced a backward-incompatible fix to macros containing a '#'. While
the above use of '#', a simple Make variable, still needs to be escaped,
a '#' within a function invocation doesn't need to be escaped anymore.
As Martin Dorey explained on the GNU Make discussion [1], the above
declaration is generated from make-cmd, defined as:

	make-cmd = $(subst \#,\\\#,$(subst $$,$$$$,$(call escsq,$(cmd_$(1))))

Since GNU Make 4.3, the first argument of subst should not have a
backslash. make-cmd now looks for literally \# and doesn't find it, and
as a result doesn't add the backslash when generating .o.cmd files.

[1] http://savannah.gnu.org/bugs/?20513

We could fix it by changing make-cmd to "$(subst #,\#,...)", but to
avoid compatibility headaches, simply get rid of the KBUILD_STR
definition, as done in Linux by b42841b7bb62 ("kbuild: Get rid of
KBUILD_STR"). Quote the string arguments directly rather than asking the
preprocessor to quote them.

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: Denys Vlasenko <vda.linux@googlemail.com>

1 files changed, 4 insertions, 4 deletions

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 3e54ea7..d8d768a 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -81,10 +81,10 @@ obj-dirs	:= $(addprefix $(obj)/,$(obj-dirs))
 # Note: It's possible that one object gets potentially linked into more
 #       than one module. In that case KBUILD_MODNAME will be set to foo_bar,
 #       where foo and bar are the name of the modules.
-name-fix = $(subst $(comma),_,$(subst -,_,$1))
-basename_flags = -D"KBUILD_BASENAME=KBUILD_STR($(call name-fix,$(*F)))"
+name-fix = $(squote)$(quote)$(subst $(comma),_,$(subst -,_,$1))$(quote)$(squote)
+basename_flags = -DKBUILD_BASENAME=$(call name-fix,$(*F))
 modname_flags  = $(if $(filter 1,$(words $(modname))),\
-                 -D"KBUILD_MODNAME=KBUILD_STR($(call name-fix,$(modname)))")
+                 -DKBUILD_MODNAME=$(call name-fix,$(modname)))
 
 _c_flags       = $(CFLAGS) $(EXTRA_CFLAGS) $(CFLAGS_$(*F).o)
 _a_flags       = $(AFLAGS) $(EXTRA_AFLAGS) $(AFLAGS_$(*F).o)
@@ -110,7 +110,7 @@ endif
 
 c_flags        = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(CPPFLAGS) \
 		 $(__c_flags) $(modkern_cflags) \
-		 -D"KBUILD_STR(s)=\#s" $(basename_flags) $(modname_flags)
+		 $(basename_flags) $(modname_flags)
 
 a_flags        = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(CPPFLAGS) \
 		 $(__a_flags) $(modkern_aflags)